Packaging substrate, method for manufacturing same, and chip packaging structure having same

ABSTRACT

A packaging substrate includes a circuit board, a number of first conductive posts, and a number of second conductive posts. The circuit board includes a first base and a first conductive pattern layer formed on a first surface of the first base. The first conductive posts extend from and are electrically connected to the first conductive pattern layer. The second conductive posts extend from and are electrically connected to the first conductive pattern layer. The height of each of the second conductive posts is larger than that of each of the first conductive posts. A manufacturing method thereof is also provided.

CROSS-REFERENCE TO RELATED APPLICATIONS

This patent application is a divisional application of patentapplication Ser. No. 14/097,251, filed on Dec. 5, 2013, entitled“PACKAGING SUBSTRATE, METHOD FOR MANUFACTURING SAME, AND CHIP PACKAGINGSTRUCTURE HAVING SAME”, assigned to the same assignee, which is based onand claims priority from China Patent Application No. 2012-10582244.6,filed in China on Dec. 28, 2012, and disclosures of both relatedapplications are incorporated herein by reference in their entireties.

FIELD

The present disclosure relates to semiconductor packaging technologyand, particularly, to a packaging substrate, a method for manufacturingthe packaging substrate, and a chip package structure having thepackaging substrate.

BACKGROUND

A chip packaging structure includes a packaging substrate, a connectingsubstrate, and a number of chips. Some of the chips are arranged on andare electrically connected to the packaging substrate, and the otherchips are arranged on and are electrically connected to the connectingsubstrate. The packaging substrate is mechanically and electricallyconnected to the connecting substrate through a number of solder balls,which are between one surface of the packaging substrate and an opposingsurface of the connecting surface. However, the binding force betweenthe packaging substrate and the connecting surface is limited becausethe contact areas between the solder balls and the surfaces are limited.Thus, the solder balls are easily damaged or dislodged if the chippackaging structure is touched when in transport or in use. This reducesthe performance and safety of the chip packaging structure.

Therefore, it is desirable to provide a packaging substrate, a methodfor manufacturing the packaging substrate, and a chip packagingstructure having the packaging substrate, to overcome or at leastalleviate the above-mentioned problems.

BRIEF DESCRIPTION OF THE DRAWINGS

Implementations of the present technology will now be described, by wayof example only, with reference to the attached figures.

FIG. 1 shows a cross sectional view of a circuit board for a method ofmanufacturing a packaging substrate according to a first exemplaryembodiment.

FIG. 2 shows a cross sectional view of a circuit board in FIG. 1 afterforming a metal layer.

FIG. 3 shows a cross sectional view of a circuit board in FIG. 2 afterforming a first plating barrier pattern.

FIG. 4 shows a cross sectional view of a circuit board in FIG. 3 afterforming a first plating layer.

FIG. 5 shows a cross sectional view of a circuit board in FIG. 4 afterforming a second plating barrier pattern on the first plating layer.

FIG. 6 shows a cross section view of a circuit board in FIG. 5 afterforming a first etching barrier pattern.

FIG. 7 shows a cross sectional view of a circuit board in FIG. 6 afterremoving the second plating barrier pattern.

FIG. 8 shows a cross sectional view of a circuit board in FIG. 7 afterforming a second plating layer on the first plating layer and the firstetching barrier pattern.

FIG. 9 shows a cross sectional view of a circuit board in FIG. 8 afterforming a second etching barrier pattern on the second plating layer.

FIG. 10 shows a cross sectional view of a circuit board in FIG. 9 afteretching the first plating layer and the second plating layer to form thefirst conductive posts and the second conductive posts.

FIG. 11 shows a cross sectional view of a circuit board in FIG. 10 afterremoving the first plating barrier pattern, the first etching barrierpattern, and the second etching barrier pattern.

FIG. 12 is a diagrammatic view of an alternative embodiment of thepackaging substrate in FIG. 10 after removing the first etching barrierpattern and the second etching barrier pattern and melting the firstetching barrier pattern to form solder caps.

FIG. 13 shows a cross sectional view of a circuit board in FIG. 8 afterforming a photoresist layer for a method of manufacturing a packagesubstrate according to a second exemplary embodiment.

FIG. 14 shows a cross sectional view of a circuit board in FIG. 13 afterforming a second etching barrier pattern and a protective layer.

FIG. 15 shows a cross sectional view of a circuit board in FIG. 14 afterremoving the photoresist layer and the first plating barrier pattern andetching the first plating layer and the second plating layer to form thefirst conductive posts and the second conductive posts.

FIG. 16 is similar to FIG. 12, but showing another embodiment of thepackaging substrate.

FIG. 17 is a cross-sectional view of a chip packaging structure,according to a third exemplary embodiment.

DETAILED DESCRIPTION

Referring to FIGS. 1-11, a method for manufacturing a packagingsubstrate 100 a, according to a first exemplary embodiment, is shown.The method includes the following steps.

Referring to FIG. 1, a circuit board 110 is provided.

The circuit board 110 may be a single-sided circuit board, adouble-sided circuit board, or a multilayer circuit board. The circuitboard 110 includes a first base 111, a first conductive pattern layer112, a second conductive pattern layer 113, a first solder mask 114, anda second solder mask 115. In at least one embodiment, the circuit board110 is a multilayer circuit board, and includes a number of resin layers(not shown) and a number of conductive pattern layers (not shown)alternately stacked on one another.

The first base 111 includes a first surface 1111 and a second surface1112. The first surface 1111 and the second surface 1112 are positionedat opposite sides of the first base 111, and the first surface 1111 issubstantially parallel to the second surface 1112. The first conductivepattern layer 112 is located on the first surface 1111. The secondconductive pattern layer 113 is located on the second surface 1112. Thefirst conductive pattern layer 112 is electrically connected to thesecond conductive pattern layer 113 through via holes (not shown)defined in the first base 111.

The first solder mask 114 covers part of the first surface 1111 which isexposed to the first conductive pattern layer 112, and part of the firstconductive pattern layer 112. The first solder mask 114 defines a numberof first openings 1141 and a number of second openings 1142. The firstopenings 1141 are positioned at a central portion of the first soldermask 114 and are arranged in an array. The second openings 1142 surroundthe first openings 1141. The cross-sectional area of each of the firstopenings 1141 is less than that of each of the second openings 1142. Thefirst conductive pattern layer 112 is exposed to the first openings 1141and the second openings 1142.

The second solder mask 115 covers part of the second surface 1112 whichis exposed to the second conductive pattern layer 113, and part of thesecond conductive pattern layer 113. The second solder mask 115 definesa number of third openings 1151. The second conductive pattern layer 113is exposed to the third openings 1151.

Referring to FIG. 2, a metal layer 120 is formed on the first soldermask 114. The metal layer 120 is copper and serves as a seed layer. Inat least one embodiment, the metal layer 120 is formed by a sputteringcoating process.

Referring to FIG. 3, a first plating barrier pattern 130 is formed onthe second solder mask 115 and on the part of the second conductivepattern layer 113 which is exposed to the second solder mask 115. In atleast one embodiment, the first plating barrier pattern 130 is formed bya printing stripping rubber method.

Referring to FIG. 4, a first plating layer 140 is formed on the metallayer 120 and the first conductive pattern layer 112. The first platinglayer 140 covers the entire metal layer 120 and the part of the firstconductive pattern layer 112 which is exposed to the first openings 1141and the second openings 1142. In at least one embodiment, the firstplating layer 140 is made of copper.

Referring to FIG. 5, a second plating barrier pattern 150 is formed onthe first plating layer 140. The second plating barrier pattern 150defines a number of first through holes 151 corresponding to the firstopenings 1141. The first through holes 151 are arranged in an array andcorrespond to pads of a chip to be packaged (not shown). The firstthrough holes 151 may be formed by laser beams.

Referring to FIG. 6, a first etching barrier pattern 160 is formed onthe part of the first plating layer 140 which is exposed to the firstthrough holes 151, by a plating method. The first etching barrierpattern 160 corresponds to the first through holes 151. In at least oneembodiment, the first etching barrier pattern 160 may be made of tin ornickel. That is, the first etching barrier pattern 160 does not reactwith an etching agent which can etch away copper. Thus, the part of thefirst plating layer 140 covered by the first etching barrier pattern 160can be maintained when the first plating layer 140 is etched by theetching agent. The first etching barrier pattern 160 may be made ofother metal which does not react with the etching agent.

Referring to FIGS. 6-7, the second plating barrier pattern 150 isremoved by stripping.

Referring to FIG. 8, a second plating layer 170 is formed on the firstplating layer 140 and the first etching barrier pattern 160 by plating.In at least one embodiment, the second plating layer 170 is made ofcopper. The thickness of the second plating layer 170 is larger thanthat of the first etching barrier pattern 160. That is, the firstetching barrier pattern 160 is entirely packaged within the secondplating layer 170.

Referring to FIG. 9, a second etching barrier pattern 180 correspondingto the second openings 1142 is formed on the second plating layer 170. Adry film is first attached on the second plating layer 170, and thenexposed and developed, thereby the second etching barrier pattern 180 isformed.

Referring to FIG. 10, the first plating layer 140 and the second platinglayer 170 are etched to form a number of first conductive posts 191 anda number of second conductive posts 192, using an etching agent. Thefirst conductive post 191 includes the part of the first plating layer140 which is shielded by the first etching barrier pattern 160. Thesecond conductive post 192 includes the parts of the first and secondplating layers 140 and 170 which are shielded by the second etchingbarrier pattern 180. In at least one embodiment, the etching factor isgreater than four, for reducing lateral erosion. The first conductiveposts 191 are located in the first openings 1141 and the secondconductive posts 192 are located in the second openings 1142. The heightof each first conductive post 191 is equal to the thickness of the firstplating layer 140. The height of each second conductive post 192 isequal to the sum of the thicknesses of the first plating layer 140 andof the second plating layer 170.

Referring to FIGS. 10-11, the first plating barrier pattern 130, thefirst etching barrier pattern 160, and the second etching barrierpattern 180 are removed to form the packaging substrate 100 a. In otherembodiments, referring to FIG. 10 together with FIG. 12, the firstetching barrier pattern 160 does not need to be removed. Instead, thefirst etching barrier pattern 160 is made molten to form solder caps 193using an IR-reflow soldering process. The solder caps 193 are configuredto protect part of the first conductive pattern layer 112 correspondingto the solder caps 193.

Referring to FIGS. 1-8 and 13-15, a method for manufacturing a packagingsubstrate 100 b according to a second exemplary embodiment is shown. Thefirst to eighth steps in at least one embodiment are the same as thefirst to eighth steps in the first embodiment. Thus, the explanation forthe method of the second embodiment begins with the ninth step.

Referring to FIG. 13, a photoresist layer 171 with a number of secondthrough holes 172 is formed on the second plating layer 170 and a numberof third through holes 131 are defined in the first plating barrierpattern 130. The second through holes 172 correspond to the secondopenings 1142.

Referring to FIG. 14, a second etching barrier pattern 180 is formed onthe part of the second plating layer 170 which is exposed to the secondthrough holes 172 and a protective layer 194 is formed on the part ofthe second conductive pattern layer 113 which is exposed to the thirdthrough holes 131. In at least one embodiment, the second etchingbarrier pattern 180 and the protective layer 194 are gold plated overnickel and are formed by plating. That is, the second etching barrierpattern 180 serves as a protective layer.

Referring to FIGS. 14-15, the photoresist layer 171 and the firstplating barrier pattern 130 are removed. The first plating layer 140 andthe second plating layer 170 are etched to form a number of firstconductive posts 191 and a number of second conductive posts 192, andthereby the packaging substrate 100 b is formed. The first etchingbarrier pattern 160 is located on a top end of each of the firstconductive posts 191, and the second etching barrier pattern 180 ispositioned on a top end of each of the second conductive posts 192. Thefirst etching barrier pattern 160 thus cooperates with the secondetching barrier pattern 180 to protect the first conductive patternlayer 112. The protective layer 194 is configured to protect the secondconductive pattern layer 113. In other embodiments, referring to FIG. 16together with FIG. 15, the first etching barrier pattern 160 can be mademolten to form solder caps 193 using an IR-reflow soldering process.

Referring to FIG. 12, a packaging substrate 100 a, according to a thirdexemplary embodiment, is shown. The packaging substrate 100 a includes acircuit board 110, a number of first conductive posts 191, and a numberof second conductive posts 192.

The circuit board 110 may be a single-sided circuit board, adouble-sided circuit board, or a multilayer circuit board. The circuitboard 110 includes a first base 111, a first conductive pattern layer112, a second conductive pattern layer 113, a first solder mask 114, anda second solder mask 115. In at least one embodiment, the circuit board110 is a multilayer circuit board, and includes a number of resin layers(not shown) and a number of conductive pattern layers (not shown)alternately stacked on one another.

The first base 111 includes a first surface 1111 and a second surface1112. The first surface 1111 and the second surface 1112 are positionedat opposite sides of the first base 111, and the first surface 1111 issubstantially parallel to the second surface 1112. The first conductivepattern layer 112 is located on the first surface 1111. The secondconductive pattern layer 113 is located on the second surface 1112. Thefirst conductive pattern layer 112 is electrically connected to thesecond conductive pattern layer 113 through via holes (not shown)defined in the first base 111.

The first solder mask 114 covers the part of the first surface 1111which is exposed to the first conductive pattern layer 112 and part ofthe first conductive pattern layer 112. The first solder mask 114defines a number of first openings 1141 and a number of second openings1142. The first openings 1141 are positioned at a central portion of thefirst solder mask 114 and are arranged in an array. The second openings1142 surround the first openings 1141. The cross-sectional area of eachfirst opening 1141 is less than that of each second opening 1142. Thefirst conductive pattern layer 112 is exposed to the first openings 1141and the second openings 1142.

The second solder mask 115 covers the part of the second surface 1112which is exposed to the second conductive pattern layer 113 and part ofthe second conductive pattern layer 113. The second solder mask 115defines a number of third openings 1151. The second conductive patternlayer 113 is exposed to the third openings 1151.

The first conductive posts 191 correspond to the first openings 1141.The second conductive posts 192 correspond to the second openings 1142.The first conductive posts 191 extend from the first conductive patternlayer 112 in the first openings 1141. The second conductive posts 192extend from the first conductive patter layer 112 in the second openings1142. The height of each second conductive post 192 is larger than thatof each first conductive post 191. A solder cap 193 is formed on a topend of each first conductive post 191. The solder cap 193 is made of tinor nickel. In other embodiments, a protective layer (not shown) can beformed on a top end of each second conductive post 192, and theprotective layer is gold plated over nickel.

Referring to FIG. 17, a chip packaging structure 10, according to afourth exemplary embodiment, is shown. The chip packaging structure 10includes a first chip packaging body 11 and a second chip packaging body12.

The first chip packaging body 11 includes the packaging substrate 100 aof the first embodiment and a first chip 200. The first chip 200includes a first top surface 201 and a first bottom surface 202. Thefirst top surface 201 and the first bottom surface 202 are positioned atopposite sides of the first chip 200. The first top surface 201 issubstantially parallel to the first bottom surface 202. A number offirst electrode pads 210 are arranged on the first bottom surface 202and correspond to the first conductive posts 191. The first chip 200 issupported on the first conductive posts 191. Each first electrode pad210 contacts a first conductive post 191, and a first solder ball 101surrounds the entire circumferential surface of a first conductive post191 and a first electrode pad 210. Thus, the first chip 200 ismechanically and electrically connected to the packaging substrate 100a. A first packaging glue 102 is infilled into a gap between the firstchip 200 and the packaging substrate 100 a to render the connectionbetween the first chip 200 and the packaging substrate 100 a morereliable.

The second chip packaging body 12 includes a connecting substrate 300, asecond chip 400, and a third chip 500. The connecting substrate 300includes a second base 310, a number of first contact pads 320, a numberof second contact pads 330, a third solder mask 340, and a fourth soldermask 350.

The second base 310 includes a second top surface 3101 and a secondbottom surface 3102. The second top surface 3101 and the second bottomsurface 3102 are positioned at opposite sides of the second base 310,and the second top surface 3101 is substantially parallel to the secondbottom surface 3102. The second base 310 defines a number of conductiveholes 340 corresponding to the second conductive posts 192, the firstcontact pads 320, and the second contact pads 330. Each of theconductive holes 340 passes through the second top surface 3101 and thesecond bottom surface 3102.

The first contact pads 320 are formed on the second top surface 3101 andaligned with the conductive holes 340. The second contact pads 330 areformed on the second bottom surface 3102 and aligned with the conductiveholes 340. That is, the first contact pads 320 are electricallyconnected to the second contact pads 330 through the conductive holes340.

The third solder mask 350 is formed on the second top surface 3101 anddefines a number of fourth opening 352 corresponding to the firstcontact pads 320. Each of the first contact pads 320 is exposed to afourth opening 352. The fourth solder mask 360 is formed on the secondbottom surface 3102 and defines a number of fifth openings 362corresponding to the second contact pads 330. Each of the second contactpads 330 is exposed to a fifth opening 362.

The second chip 400 is located on the third solder mask 350 by a secondpackaging glue 600. The third chip 500 is located on the second chip 400by a dielectric film 700 and is spaced apart from the second chip 400. Anumber of second electrode pads 410 are formed on the second chip 400surrounding the second packaging glue 600. A number of third electrodepads 510 are formed on the third chip 500 surrounding the dielectricfilm 700. The second electrode pads 410 and the third electrode pads 510are electrically connected to the first contact pads 320 through wires800. A third packaging glue 105 is formed on the connecting substrate300 to seal the entire second chip 400, the entire third chip 500, theentire second solder mask 350, and the entirety of wires 800, thereforethe connections between the second chip 400, the third chip 500, and theconnecting substrate 300 are more reliable.

When the second chip packaging body 12 is packaged on the first chippackaging body 11, the second conductive posts 192 are mechanically andelectrically connected to the second contact pads 330 through secondsolder balls 103. Each second solder ball 103 surrounds the entirecircumferential surface of a second conductive post 192 and covers anentire second contact pad 330. In at least one embodiment, a number ofthird solder balls 106 are formed on the second conductive pattern layer113 exposed within the third openings 1151. The third solder balls 106are configured for connecting other electronic elements (not shown). Inat least one embodiment, sum of the height of each first conductive post191 and the thickness of the first chip 200 is equal to the height ofeach second conductive post 192.

In the chip packaging structure 10, the contact area between the firstchip 200 and the first packaging substrate 100 a is increased becausethe first solder ball 101 surrounds the entire circumferential surfaceof each first conductive post 191 and each first electrode pad 210. Thecontact area between the first chip packaging body 11 and the secondchip packaging body 12 is increased because each second solder ball 103surrounds the entire circumferential surface of each second conductivepost 192 and covers the entirety of each second contact pad 330.Therefore the first and second solder balls 101 and 103 are morereliable in function and strength even if the chip packaging structure10 is touched when in transport or in use.

In other embodiments, the packaging substrate 100 b in the secondembodiment can be applied in the chip packaging structure 10 instead ofapplying the packaging substrate 100 a of the first embodiment.

Even though numerous characteristics and advantages of the presentembodiments have been set forth in the foregoing description, togetherwith details of the structures and functions of the embodiments, thedisclosure is illustrative only, and changes may be made in detail,especially in the matters of shape, size, and arrangement of partswithin the principles of the disclosure to the full extent indicated bythe broad general meaning of the terms in which the appended claims areexpressed.

What is claimed is:
 1. A packaging substrate comprising: a circuit boardcomprising a first base and a first conductive pattern layer formed on afirst surface of the first base; a plurality of first conductive postsextending from and electrically connected to the first conductivepattern layer; and a plurality of second conductive posts extending fromand electrically connected to the first conductive pattern layer, theheight of each of the second conductive posts being larger than that ofeach of the first conductive posts.
 2. The packaging substrate of claim1, wherein a solder cap is formed on a top end of each of the firstconductive posts.
 3. The packaging substrate of claim 1, wherein aprotective layer is formed on a top end of each of the second conductiveposts, and the protective layer is gold plating over nickel.
 4. Thepackaging substrate of claim 1, wherein the circuit board furthercomprises a first solder mask covering part of the first surface exposedto the first conductive pattern layer and part of the first conductivepattern layer, the first solder mask defines a plurality of firstopenings corresponding to the first conductive posts and a plurality ofsecond openings corresponding to the second conductive posts, the firstconductive posts are located in the respective first openings, and thesecond conductive posts are located in the respective second openings.5. The packaging substrate of claim 4, wherein the circuit board furthercomprises a second conductive pattern layer formed on an opposing secondsurface of the first base and a second solder mask, the second soldermask defines a plurality of third openings, part of the secondconductive pattern layer is exposed to the third openings.
 6. Thepackaging substrate of claim 5, wherein a protective layer is formed onthe part of the second conductive pattern layer exposed to the thirdopenings.
 7. The packaging substrate of claim 1, wherein the firstconductive posts are located at a central portion of the firstconductive pattern layer, and the second conductive posts surround thefirst conductive posts.
 8. A chip packaging structure comprising: afirst chip packaging body comprising a packaging substrate and a firstchip, the packaging substrate comprising: a circuit board comprising afirst base and a first conductive pattern layer formed on a firstsurface of the first base; a plurality of first conductive postsextending from and electrically connected to the first conductivepattern layer; and a plurality of second conductive posts extending fromand electrically connected to the first conductive pattern layer, theheight of each of the second conductive posts being larger than that ofeach of the first conductive posts; the first chip comprising aplurality of first electrode pads corresponding to the first conductiveposts, the first electrode pads mechanically and electrically connectedto the respective first conductive posts through first solder balls; anda second chip packaging body comprising a connecting substrate and asecond chip packaged on the connecting substrate, the connectingsubstrate comprising a plurality of first contact pads corresponding tothe second conductive posts, and the first contact pads mechanically andelectrically connected to the respective second conductive posts throughsecond solder balls.
 9. The chip packaging structure of claim 8, whereina sum of the height of each of the first conductive posts and thethickness of the first chip is equal to the height of each of the secondconductive posts.
 10. The chip packaging structure of claim 9, wherein asolder cap is formed on a top end of each of the first conductive posts.11. The chip packaging structure of claim 9, wherein a protective layeris formed on a top end of each of the second conductive posts, and theprotective layer is gold plating over nickel.
 12. The chip packagingstructure of claim 9, wherein the circuit board further comprises afirst solder mask covering part of the first surface exposed to thefirst conductive pattern layer and part of the first conductive patternlayer, the first solder mask defines a plurality of first openingscorresponding to the first conductive posts and a plurality of secondopenings corresponding to the second conductive posts, the firstconductive posts are located in the respective first openings, and thesecond conductive posts are located in the respective second openings.13. The chip packaging structure of claim 12, wherein the circuit boardfurther comprises a second conductive pattern layer formed on anopposing second surface of the first base and a second solder mask, thesecond solder mask defines a plurality of third openings, part of thesecond conductive pattern layer is exposed to the third openings. 14.The chip packaging structure of claim 13, wherein a protective layer isformed on the part of the second conductive pattern layer exposed to thethird openings.
 15. The chip packaging structure of claim 9, wherein thefirst conductive posts are located at a central portion of the firstconductive pattern layer, and the second conductive posts surround thefirst conductive posts.